Reltech provides the full spectrum of semiconductor reliability qualification services — from die-level wearout testing to board-level environmental stress — all executed to JEDEC JESD22, AEC Q-100, MIL-STD-883, and IEC 60068 standards.
– Life & Operating Stress
The cornerstone of every qualification programme — quantifying device reliability under elevated stress conditions to project field lifetime and FIT rates.
Stresses devices under elevated temperature and voltage bias to characterise intrinsic wearout failure mechanisms — TDDB, hot carrier injection, electromigration, and NBTI.
Conducted per JEDEC JESD22-A108 at stress temperatures of 125–150°C. Failure rate data enables FIT calculation using Arrhenius acceleration modelling and supports AEC Q-100 Grade 0–3 qualification. Reltech’s 8000 Series HTOL systems provide automated, multi-channel test capability with individual device-level data logging.
Operating life stress at sub-ambient temperatures to characterise cold-temperature failure mechanisms in devices requiring full extended temperature range validation.
Executed per JEDEC JESD22-A119 at temperatures down to -55°C under defined bias conditions. Critical for AEC Q-100 Grade 0 and Grade 1 qualification, LTOL supports lifetime projection for devices operating continuously at low ambient temperatures including Automotive underhood and Aerospace avionics applications.
Characterises the early failure population of a device lot — distinguishing infant mortality defects from intrinsic wearout to define effective burn-in screen criteria.
Conducted per JEDEC JESD47 stress test qualification guidelines. ELFR data underpins burn-in screen optimisation, allowing customers to demonstrate outgoing quality without over-stressing known-good devices. Results feed directly into FIT rate reporting and reliability prediction models.
Production-level defect screening under elevated temperature and voltage to remove infant mortality failures before devices ship to customers.
Dynamic and static burn-in programmes executed in Reltech 7000 Series ovens. Burn-in parameters are defined per device stress audit to maximise defect detection without degrading known-good devices. Combined with final electrical test to deliver outgoing quality levels compliant with customer AQL requirements.
– Moisture & Environmental
Evaluating package integrity and corrosion susceptibility under defined humidity, temperature, and bias conditions to the leading international standards.
Pressure-accelerated moisture ingress and corrosion testing under bias — typically 130°C/85%RH — providing a compressed-time alternative to THB for package qualification.
Executed per JEDEC JESD22-A110 in a pressurised HAST chamber. Acceleration factors of approximately 50–100x over standard THB conditions make HAST the preferred moisture stress test in AEC Q-100 qualification flows. Reltech provides biased HAST per A110 and unbiased uHAST variants.
Unbiased pressurised moisture soak for packages where electrical bias cannot be applied — evaluating moisture diffusion and corrosion in passive structures and passivation layers.
Per JEDEC JESD22-A118 at 130°C/85%RH without bias. Commonly used as a preconditioning assessment tool and as a stand-alone moisture sensitivity indicator for passive components and MCM packages.
Long-duration 85°C/85%RH moisture and corrosion stress under bias — the original humidity reliability test, still widely specified for consumer and telecom device qualification.
Performed per JEDEC JESD22-A101. Typical durations of 500 or 1,000 hours at 85°C/85%RH under voltage bias. Results feed AEC Q-100 qualification reports and moisture lifetime modelling to IPC/JEDEC J-STD-020. Often combined with interim electrical measurements at 168-hour intervals.
– Thermal & Mechanical
Cyclic thermal excursions between temperature extremes to assess solder joint fatigue, die attach delamination, and package structural integrity under thermomechanical stress.
Per JEDEC JESD22-A104, Conditions A through G. Reltech supports air-to-air cycling with dwell times and ramp rates tailored to device structure. Results characterise CTE mismatch fatigue and feed Coffin-Manson lifetime models for AEC Q-100 qualification. Typical programmes: 500, 1,000, or 2,000 cycles.
Thermomechanical fatigue driven by self-heating under pulsed power — assessing bond wire, die attach, and substrate fatigue in power devices under realistic operating profiles.
Key for IGBTs, MOSFETs, and GaN/SiC power devices where junction temperature swings under load are the primary reliability driver. Power cycling captures fatigue mechanisms that temperature cycling in an oven cannot replicate, as it exercises the actual thermal path through the device.
Moisture soak and reflow simulation to assess package integrity and MSL classification prior to reliability stress programmes.
Per IPC/JEDEC J-STD-020. MSL Level 1 through 6 classification. Full sequence: moisture soak, reflow cycles, intermediate and final electrical test. Essential precursor to HTOL, HAST, THB, and TC qualification stress programmes. SAM inspection post-reflow available.
– Electrical & Analytical
Human Body Model (HBM) and Charged Device Model (CDM) ESD qualification to characterise device robustness to electrostatic discharge events during manufacturing and field handling.
HBM per JEDEC JESD22-A114; CDM per JESD22-C101. ESD testing determines device classification level and identifies weak structures requiring design hardening. Results required for AEC Q-100 Grade qualification. Reltech provides full pin matrix testing with pass/fail classification per JEDEC ESD sensitivity levels.
Characterises susceptibility to latch-up — a potentially destructive thyristor-like condition triggered by transient supply or I/O overvoltage events in CMOS devices.
Per JEDEC JESD78. Latch-up testing is mandatory in AEC Q-100 qualification and increasingly required for industrial and medical device qualification. Tests are performed at 125°C to capture worst-case latch-up susceptibility. Reltech provides I-V characterisation and trigger current/voltage classification.
Scanning acoustic microscopy (SAM) for non-destructive delamination and void detection, combined with failure analysis to identify root cause mechanisms in failed or suspicious devices.
SAM inspection per JEDEC JESD22-B112 and MIL-STD-2132. Identifies die attach delamination, package cracking, and moisture-induced voiding before and after reliability stress. Failure analysis services include decapsulation, optical and SEM inspection, and cross-section analysis to support corrective action reporting.
Our engineers can review your device specification, application, and target markets to recommend the right qualification programme — before you commit to a quote.
